1. Field of the Disclosure
The present disclosure generally relates to a semiconductor device structure, and, more particularly, to a semiconductor device structure capable of compensating for temperature effects of semiconductor devices in SOI technologies.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. Particularly, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes ranging even into the deep sub-micron regime; the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 10 nm. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs can be made much smaller than discreet circuits composed of independent circuit components. The majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or simply MOS transistors), and passive elements, such as resistors and capacitors, integrated on a semiconductor substrate with a given surface area. Typically, present-day integrated circuits involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a FET or a MOSFET is that of an electronic switching element, wherein a current through a channel region between two contact regions, referred to as source and drain, is controlled by a gate electrode, which is disposed over the channel region and to which a voltage relative to source and drain is applied. Particularly, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of a MOSFET is changed and the characteristic voltage level, usually called “threshold voltage,” and in the following referred to as “Vt”, characterizes the switching behavior of a MOSFET. In general, Vt depends nontrivially on the transistor's properties, e.g., materials, dimensions, etc., such that the implementation of a desired Vt involves plural steps of adjustment and fine-tuning during the fabrication process.
With the continuous scaling down to increasingly small technology nodes in the deep sub-micron regime (at present at 22 nm and beyond), various issues and challenges arise. For example, a precise control of the electrical conductivity of the channel of a MOS transistor is difficult to maintain at very small process geometries. Since the switching behavior of a MOSFET is characterized by the threshold voltage (Vt) of a MOSFET, the precise setting of a definition and control of the threshold voltage (Vt) throughout the fabrication process of semiconductor devices is essential for achieving optimal power consumption and performance of semiconductor device structures. In general, there are several factors which control the threshold voltage (Vt), such as the gate oxide thickness, the work function of the gate and the channel doping, mainly representing independent factors. The scaling of a semiconductor device to more advanced technology nodes led to faster switching and higher current drive behaviors of advanced semiconductor devices, at the expense, however, of a decreased noise margin, increased leakage current and increased power.
Currently, the most common digital integrated circuits built today use CMOS technology, which is fast and offers a high circuit density and low power per gate. CMOS devices or “complementary symmetry metal oxide semiconductor” devices, as sometimes referred to, make use of complementary and symmetrical pairs of P-type and N-type MOSFETs. Two important characteristics of CMOS devices are the high noise immunity and low static power consumption of a CMOS device because the series combination of complementary MOSFETs in a CMOS device draws significant power only momentarily during switching between on- and off-states, since one transistor of a CMOS device is always in the off-state. Consequently, CMOS devices do not produce as much waste heat as other forms of semiconductor devices, for example, transistor-transistor logic (TTL) or NMOS logic devices, which normally have some standing current even when not changing state. In current CMOS technologies, standard transistors and IO devices have the same high-k dielectric and metal electrode, whereas, in comparison with standard devices, the SiO2 oxide of IO devices is thicker.
In general, a MOSFET as fabricated by SOI techniques is a semiconductor device (MOSFET) in which a semiconductor layer (sometime referred to as an active layer), such as silicon, germanium or silicon germanium, is formed on an insulator layer, e.g., a buried oxide (BOX) layer, which is in turn formed on a semiconductor substrate. Conventionally, there are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For example, in an N-type PDSOI MOSFET, a P-type film being sandwiched between a gate oxide (GOX) and a buried oxide (BOX) is so large that the depletion region cannot cover the whole P-region. Therefore, to some extent, PDSOI devices behave like bulk MOSFETs. In an FDSOI device, the depletion region covers the whole semiconductor layer. As the GOX in FDSOI techniques supports fewer depletion charges than the bulk, an increase in inversion charges occurs in the fully depleted semiconductor layer, resulting in higher switching speeds.
In recent attempts to provide a simple way of meeting power/performance targets, back-biasing was suggested for SOI devices, e.g., in FDSOI devices. Herein, back-biasing consists of applying a voltage just under the BOX of target semiconductor devices. In doing so, the electrostatic control of the semiconductor device is changed and the threshold voltage is shifted to either obtain more drive current (hence, higher performance) at the expense of increased leakage current (forward back bias (FBB)) or to cut leakage current at the expense of reduced performance. While back biasing in planar FDSOI techniques is somewhat similar to body biasing as implemented in bulk CMOS technologies, it offers a number of key advantages in terms of level of efficiency of the bias that may be applied. For example, back-biasing can be utilized in a dynamic way on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue.
In typical low voltage applications, the Vt of FET devices is at about 0.2 V. In low standby power/low leakage applications, supply voltages to FET devices may be in the range of about 0.8-1.1 V.
Upon temperature changes, Vt changes and variations in Vt in the range of about 0.8 mV/K are observed. Exposing semiconductor devices to variations in the temperature, Vt may be subjected to unacceptable variations caused by such changes in the temperature. For example, assuming a temperature range in which FET devices may be operated, e.g., between −5° C. and +125° C., deviations of Vt on the order of up to 40% and more may be expected.
In view of the above-described situation, it is desirable to provide a semiconductor device structure that is capable of compensating for temperature effects on a semiconductor device comprised of the semiconductor device structure in the context of SOI techniques, such as FDSOI devices, at advanced technology nodes of 28 nm and beyond.